1. Field of the Invention
The present invention relates to microprocessors and more particularly to a method and mechanism for directly determining a CPU's bus-to-core frequency ratio in a computer system.
2. Prior Art
Most current microprocessors have a mechanism by which they can set their bus-to-core frequency ratio. This function helps the microprocessor to run faster than the computer system in which it is operating by having the CPU run at a higher clock frequency internally than the operating frequency on the bus. The ratio is set by using one or more external pins which the CPU samples at RESET. But, presently the CPU does not provide any mechanism by which the software can determine the ratio. The ratio relationship can be represented by the equation: EQU F=n.times.f
where
F=core frequency PA1 f=bus frequency PA1 n=core/bus frequency ratio, and PA1 Binary value of A1..0!=f(n), e.g., PA1 00=1.5 PA1 01=2 PA1 10=2.5 PA1 11=3
a given CPU normally has only a certain number of core-to-bus frequency ratios at which it can operate.
One present method for determining a CPU's bus-to-core frequency ratio involves guessing about the value of n. More particularly, on power up, the CPU will be executing codes entirely out of its internal cache (also known as Level-1 cache). Certain instruction sequences are repeatedly executed, typically in a program loop reside entirely inside Level-1 cache at core frequency F. The number N of such instructions successfully completed within a predetermined time T is counted. Time T can be set to some known value that is platform independent. For example, in a PC/AT or compatible system, the timer (8254C) is reset to count 0 through some I/O instruction, and the counter begins to count up. Then N instructions are executed entirely within the CPU internal cache. After these N instructions are completed, the value of the 8254 counter is read. Knowing the frequency of the clock to the 8254 counter and the count, the time required to complete the N instructions can be easily determined. The number N is directly related to the core frequency F of the CPU. A relation between N and F can therefore be determined experimentally (e.g., record N while varying F) and will be used by the BIOS to determine the core frequency F in the target system. Because the CPU can have only a certain number of core-to-bus frequency ratios, the BIOS looks at the standard ratios and makes a guess as to what the bus frequency and the ratio n actually are. Thus, for instance, in the Pentium CPU, the BIOS can allow n to be either 1.5 or 2. Accordingly, if the BIOS determines that the CPU core is running at F=100 MHz, then the CPU bus frequency f could be either 66 MHz (n=1.5) or 50 MHz (n=2). Unfortunately, the bus frequency f is also directly related to the performance of other systems so that guessing is not an optimum method for efficient operation. A DRAM controller may be able to run 6-3-3-3 at 66 MHz and 5-2-2-2 at 50 MHz, where 50 and 66 MHZ is the CPU bus frequency. The expression 6-3-3-3 means the first data transaction is completed in 6 bus clock pulses and each of the next three data transactions is completed in 3 bus clock pulses. The same applies to the 5-2-2-2 expression. This burst timing is set through certain timing registers as part of the DRAM controller during power on self-test, that is, initialization. Without knowing n (1.5 or 2), the BIOS is forced to assume that the bus speed is the higher one (e.g., 66 MHz) and set the DRAM timing to 6-3-3-3. If the assumption is right, then the DRAM will be running at 6-3-3-3 at 66 MHz. If the guess is wrong, then the DRAM will be running at 6-3-3-3 at 50 MHz. Clearly, in this case the DRAM is not running at its highest performance. Nevertheless, the system is a stable one. However, if the BIOS sets the timing register to the alternate setting (i.e., 5-2-2-2), a potential system failure may occur. Clearly, if the actual bus frequency is 50 MHz, the DRAM timing is optimized, but, if the bus frequency is 66 MHz, then the DRAM will be running at 5-2-2-2 at 66 MHz and the DRAM timing specification is violated and failure may result. It will therefore be seen that it is imperative to know the core/bus frequency ratio in order to avoid failure and to optimize system performance.
Another approach to determining the CPU's core-to-bus frequency ratio is to have an external agent, e.g., a Chipset, sample the external CPU pins which set the clock frequency ratio and latch the values into a register, which can then be read by the BIOS to determine the ratio. This arrangement may be expressed diagrammatically as shown in FIG. 1. As seen in the Figure, the ratios may be set as follows:
The disadvantage of this approach is that it is necessary to use e.g., two pins (the number of pins equivalent to the number of pins used by the CPU to do this function) on the external agent (Chipset) to determine the ratio. While this approach may work very well in determining the ratio n, it requires extra external hardware in terms of pins used by external agents (Chipsets), which additions is preferably avoided.
Problem to be Solved
It is accordingly a problem in the microprocessor art to accurately and efficiently determine a CPU's core-to-bus frequency ratio.
Objects
It is therefore an object of the present invention to provide a method and mechanism for accurately and efficiently determining the CPU core-to-bus frequency ratio in a computer system.
It is another object of the invention to provide a method and mechanism on current CPUs to accurately and efficiently determine the CPU core-to-bus frequency ratio.
It is further object of the invention to provide a direct method and mechanism on current CPUs to accurately and efficiently determine and use the core-to-bus frequency ratio in order to optimize computer system performance.